Business Wire

Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process ...
EDN

Cadence Digital and Custom/Analog Tools Achieve TSMC Certification for 16FF+ Process, Companies Collaborate on 10nm FinFET

The Cadence custom/analog and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design ...
EDN

Cadence Unveils Broad IP Portfolio for New TSMC 16nm FinFET Plus Process

Currently under development for the 16 FF+ process, the Cadence IP portfolio includes multiple high-speed protocols for several key memory, storage and interconnect standards critical in the ...
Business Wire

Cadence Collaborates With TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design

Cadence digital, signoff and custom/analog tools achieve latest DRM and SPICE certifications, and Cadence IP is enabled for TSMC 5nm process technology to advance mobile, HPC, 5G and AI application ...
Nasdaq

Cadence (CDNS) Receives Certification for Intel 16 FinFET

Cadence Design Systems CDNS announced that its digital and custom/analog flows had received certification on Intel's 16 FinFET process technology. Additionally, Cadence's design intellectual property ...
Nasdaq

GLOBALFOUNDRIES and Cadence Add Machine Learning Capabilities to DFM Signoff for GF’s Most Advanced FinFET Solutions

Cadence Litho Physical Analyzer with ML technology qualified for GF 12LP/12LP+ solutions, providing up to 33% greater detection efficiency with less than 10% runtime impact Collaboration between ...
Digi Times

HiSilicon expands adoption of Cadence tools and IP for advanced-node FinFET designs

Cadence Design Systems announced on December 1 that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for 16nm FinFET ...
Fudzilla

Cadence close to releasing DDR4 and LPDDR4 products

Cadence Design Systems says its DDR4 and LPDDR4 IP using TSMC’s 16nm FinFET Plus (16FF+) process have completed TSMC9000 Silicon Assessment. The Cadence Denali DDR controller IP, and both the Denali ...
Digi Times

Cadence digital and custom/analog tools achieve TSMC certification for 10nm FinFET early design starts

Cadence Design Systems has announced that its digital and custom/analog tools have achieved certification from TSMC for its most-current version of 10nm FinFET Design Rule Manual (DRM) and SPICE ...
Semiconductor Engineering

How Long Will FinFETs Last? (Part 3)

Semiconductor Engineering sat down to discuss how long FinFETs will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at Cadence; Juan Rey, Sr. Director of Engineering ...
Semiconductor Engineering

The Week In Review: Design

Cadence unveiled a new equivalence checking tool which features a massively parallel architecture capable of scaling to 100s of CPUs and adaptive proof technology that analyzes each partition and ...