Enables earlier narrowing down of process and device options, reducing expensive and time-consuming wafer-based iterations Allows creation of higher-quality early Process Design Kits (PDKs) for design ...

How a real chip-last process flow with a chip-to-wafer (C2W) bonding technology can address the RDL-base Interposer PoP challenge. Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has ...

Scientists from Germany’s Fraunhofer ISE – together with a consortium of plant manufacturers, metrology companies, and research institutions – have developed a new production line concept for ...

Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the ...

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LONDON — Surface Technology Systems plc, a developer of plasma etch systems, has announced that it intends to build a Deep Reactive Ion Etch (DRIE) system suitable for 300-mm diameter wafers. The ...

A research team led by Prof. Hu Weijin from the Institute of Metal Research (IMR) of the Chinese Academy of Sciences (CAS), ...